Bio: Kenneth Y. Yun joined the faculty at UCSD in 1994. He directs the Asynchronous VLSI Research Group. A member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu, he is recipient of an NSF CAREER award (1996-2000) and a 1996 Hellman Faculty Fellowship. While on the TRW technical staff, he designed numerous high-performance signal processors for spaceborne and tactical applications. He received his Ph.D. from Stanford University in 1994. While on a leave of absence from UCSD, Yun co-founded with his sister Yuni Networks, Inc., which was subsequently sold to AMCC for $240 million in stock. He returned to UCSD in 2001.
Research: Now that high-performance microprocessors have sprinted past the gigahertz mark with millions of transistors switching more than billion times per second, accounting for clock skew, signal delay, peak-power dissipation (among other phenomena), has become increasingly difficult on conventional synchronous designs, where all transistors march to the same beat. This reality makes the asynchronous alternative, Professor Yun's focus, a critical area of research. Yun is a developer of formal and automated techniques for managing multiple independently synchronized domains on a processor under a methodology in which timing and communication can be explicitly specified, synthesized, analyzed, and verified. Research areas include: mixed-timing interface design methodologies and components; specification formalism for mixed-timing interfaces; performance-driven synthesis and technology mapping techniques for mixed-timing circuits; hierarchical timing verification techniques that check the validity of assumptions used for synthesis and technology mapping; and techniques to estimate and analyze system performance. The work takes on new urgency given the shift to system-on-chip schemes.