Galton, Ian Andrew

Professor, Electrical and Computer Engineering
Division: UCSD
Phone: 858-822-1332
Fax: 858-822-3425
Room: 5606
Mail code: 407
Research Layer: Networked Infrastructure

Bio: Ian Galton joined the UCSD faculty in 1996. He manages the Integrated Signal Processing Group. Prior to coming to the Jacobs School, he was with UC Irvine, the NASA Jet Propulsion Laboratory, Acuson, and Mead Data Central. He regularly consults at several communications and semiconductor companies and teaches portions of various industry-oriented short courses on the design of data converters, PLLs, and wireless transceivers. He has served on corporate boards of directors and several corporate technical advisory boards, and been a member of the IEEE Circuits and Systems Society Board of Governors. He is Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. He received his Ph.D. in Electrical Engineering in 1992 from the California Institute of Technology.

Research: Professor Galton's main objective is to generate enabling technology for highly integrated, low-cost communication systems. His research involves the invention, development, analysis, and CMOS integrated circuit implementation of key communication system blocks such as data converters, frequency synthesizers, and clock-recovery systems. The emphasis of the research is on the development of DSP techniques to mitigate the effects of non-ideal analog circuit behavior in mixed-signal ICs. The resulting circuits tend to blur the traditionally sharp analog-digital dividing lines in communication systems in order to reduce the precision requirements of the analog circuitry. Among the enabling technologies on which he is working are: mismatch-shaping DACs (digital-to-analog converters) for high-performance delta-sigma data converters; DAC noise cancellation and interstage gain error compensation techniques in pipelined ADCs (analog-to-digital converters); Delta-sigma phase-locked loops (PLLs) for frequency-to-digital conversion and frequency synthesis; Fractional-N phase-locked loops frequency synthesis; Coupled-Oscillator clock distribution systems.